Article 7313

Title of the article

FOUNDATION OF PARALLEL-PIPELINE
VLSI STRUCTURES WITH RECONFIGURABLE MICROKERNEL ARCHITECTURE 

Authors

Osinin Il'ya Petrovich, Postgraduate student, Vyatka State University (36 Moskovskaya street, Kirov, Russia), stalker-lord@mail.ru
Knyaz'kov Vladimir Sergeevich, Doctor of engineering sciences, professor, sub-department of electronic computing machines, Vyatka State University (36 Moskovskaya street, Kirov, Russia), kniazkov@list.ru 

Index UDK

681.3.01 

Abstract

Background. At present, the capacity of the new supercomputer is growing steadily. High-productive computing is used to satisfy the growing needs of science, technology, economics, web services, energy, geophysics, and many others. Many innovative solutions aimed at improving productivity, new ways of overcoming existing limitations, particularly regarding energy consumption are fulfilled for such projects. Solution of the problem of computing speed calculation in arithmeticlogic unit (ALU) with reasonable hardware cost is the construction of the ALU, the operating part of which is a general purpose computing space, configurable to perform conveyor-parallel processing of different arithmetic and logic operations. The purpose of this paper is to study and develop ways to perform arithmetic operations with the fixed point on the basis of the modular arithmetic and ways to implement them in a uniform parallel-pipelined VLSI structures with reconfigurable microkernel architecture.
Materials and methods. To solve the problems of the given scientific foundation the theory of numbers and modular arithmetic, discrete mathematics, theory and design of computer systems for the development of new homogeneous parallel-pipelined VLSI structures, as well as the theory of mathematical modeling of computing devices and systems for evaluating their effectiveness are used.
Results. As a result evaluation of the efficiency of the proposed arithmetic unit revealed that the cost of hardware at the same speed of computation in the residual classes (RSA) after filling m+1 pipeline stages will be n/(m+1) times higher for the operations of addition and subtraction, and n2/(m+1) times higher than for the operation of multiplication and division in contrast to the positional number system (PSA), where n – bit operands, m – bit RSA residual.
Conclusions. Performing arithmetic operations in the proposed devices on the base of residual classes seems
beneficial in comparison with their positional counterparts. It is shown that the maximum parallelization of arithmetic operations is possible while using a homogeneous computing environment with a parallel-pipelined mode data. In this case, the speed of arithmetic operations such as addition, subtraction, multiplication and division is not entirely dependent on the length of operands and the response time is reduced to a cell of homogeneous computing environment. 

Key words

arithmetic unit, homogeneous computing environment, the system of residual classes, parallel-pipelined operation. 

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References

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Дата создания: 28.08.2014 14:00
Дата обновления: 28.08.2014 15:47